1. Field of the Invention
The present invention generally relates to clock generation, and more particularly to clock generation for a PCI bridge and its attached secondary buses.
2. Description of the Related Art
Most PCI (Peripheral Component Interconnect) bridges couple one secondary PCI bus to one primary PCI bus. Conventionally, clock generation for such a PCI bridge and its attached buses can be implemented using an external phase-locked loop (PLL) clock generator. A PLL clock generator is an electronic circuit which receives an input signal and generates at least an output clock signal whose frequency is the same as or multiple of that of the input signal.
An exemplary external PLL clock generator receives as input a single 33 MHz input signal and generates as output five or more in-phase clock signals having the same frequency of 33 MHz, 66 MHz, or 133 MHz. Each of these clock signals is connected to a single load. More specifically, one of these in-phase clock signals is fed to an internal PLL circuit in the PCI bridge. This internal PLL circuit in turn generates a clock signal at the same frequency for the secondary bus's logic in the PCI bridge. Each of the remaining in-phase clock signals generated by the external PLL clock generator is connected to each of the PCI Adapters attached to the secondary PCI bus. In addition, the PCI bridge includes another internal PLL circuit to generate a clock signal for the primary bus's logic in the PCI bridge. In general, a PCI adapter is an adapter whose signals and operation conform to the PCI bus standard so that the PCI card can be coupled to a PCI bus. For example, because the PCI bus standard requires 32 Address/Data (AD) signals and 4 Command/Byte Enable signals on a PCI bus, a PCI adapter must support these signals so that it can be coupled to the PCI bus. PCI adapters are used to couple external devices to the PCI bus.
In the case of a PCI bridge which couples multiple secondary PCI buses to a primary PCI bus, the clock generation scheme described above has difficulties. For example, assume a PCI bridge couples four secondary PCI buses to a primary PCI bus. These secondary PCI buses must be able to operate at different clock rates. Using the clock generation scheme described above for this PCI bridge would require four external PLL clock generators, one for each secondary PCI bus. The PCI bridge would need five internal PLL circuits for the primary PCI bus and the four secondary PCI buses. The PCI bridge would also need five independent, asynchronous islands of logic, one for each of the primary and secondary PCI buses. Current generations of chip technology do not allow the PCI bridge and that many PLL circuits in the same chip. Moreover, that many independent, asynchronous islands of logic in the PCI bridge would increase the complexity of the PCI bridge and affect its performance.
Accordingly, there is a need for an apparatus and method in which clock generation is effectively carried out for a PCI bridge and its secondary PCI buses.